Calibration technology of current mirror for high accurate voltage to current converter

The output error of the current mirror is mainly caused by three different sources of mismatch: the drain-source voltage (V_DS), the threshold voltage (V_th), and the transconductance coefficient (β). The first term V_DS mismatch is usually a deterministic error caused by finite output impedance, which can be avoided by using cascade structure and gain boosting technology. The second V_th and third β mismatches are random errors caused by the process. In order to solve the voltage to current converter accuracy and poor linearity, a current mirror calibration method combining Dynamic Element Match (DEM) and TRIM technology is proposed, this method uses TRIM technology to convert the error current between the output current mirror branch to be calibrated and the reference current mirror branch into a calibration current through a capacitor and a MOSFET, and then feedback into the output current mirror branch to be calibrated to complete the calibration, and through DEM technology switch multiple output current mirror branches to be calibrated to complete the calibration and average the output errors at the same time. Based on the SMIC 0.18μm BCD process, the circuit design of the V-I converter using DEM and TRIM technology is completed. The simulation results show that the mismatch error of the output current of the V-I converter drops from 0.12% to 0.03%, the ENOB reaches 11.2 bit, and the THD is −72.6 dB.