Optimization of signal integrity of wafer reconstruction information processing micro-module

To meet the increasing demand for highly integrated circuits, the System in Package (SiP) technology has received more and more attention. With the increase of I/O count and the increase of the data rate, the signal integrity problem in SiP has become increasingly prominent. In this paper, a form of chip-embedded fan out packaging is proposed, and the return loss of high-speed differential signals and the crosstalk of signals are studied, the layout near TSVs and solderballs, especially the return path, is optimized. As a result, S₂₁ of differential signal increases by 0.63 dB, S₁₁ decreases by 4.06 dB at the 5 GHz frequency point, near-end crosstalk of single-end signal decreases by 215 mV, and far-end crosstalk decreases by 212 mV.