晶圆重构信息处理微模组的信号完整性优化

Optimization of signal integrity of wafer reconstruction information processing micro-module

摘要: 为满足日益增长的高密度集成电路需求，立体集成的系统级封装（System in Package, SiP）技术受到了越来越多的关注。而随着I/O数量的增加和信号传输速率的不断提高，SiP封装中的信号完整性问题也变得愈发突出。本文提出一种晶圆重构立体集成形式，并针对其中的高速差分信号的反射问题和并行信号的串扰问题进行了研究，针对硅通孔（Through Silicon Via,TSV）和焊球附近的布局布线特别是返回路径进行了优化设计，使得最终高速差分信号在5 GHz频点的S₂₁上升0.63 dB，S₁₁下降了4.06 dB，单端信号的近端串扰下降了215 mV，远端串扰降低了215 mV。

Abstract: To meet the increasing demand for highly integrated circuits, the System in Package (SiP) technology has received more and more attention. With the increase of I/O count and the increase of the data rate, the signal integrity problem in SiP has become increasingly prominent. In this paper, a form of chip-embedded fan out packaging is proposed, and the return loss of high-speed differential signals and the crosstalk of signals are studied, the layout near TSVs and solderballs, especially the return path, is optimized. As a result, S₂₁ of differential signal increases by 0.63 dB, S₁₁ decreases by 4.06 dB at the 5 GHz frequency point, near-end crosstalk of single-end signal decreases by 215 mV, and far-end crosstalk decreases by 212 mV.