A proposed structure to improve SEE performance for 700 V Super-Junction VDMOS

In this paper, a new structure to improve the SEE performance for 700 V Super-Junction VDMOS is proposed. Part of the planar gate of the device is etched away, adding a Schottky contactto enhance the SEE performance.2D synopsyssentaurus TCAD is used to do simulation, and transient simulation is used to evaluate the SEE performance of the device. The simulation result shows that the overall safe working area of the device after reinforcement iseffectively increased, and the SEB and SEGR performance both improved significantly. At the same time, the electrical performance of the new structure also maintains a good level.