Design and implementation of scheduling mechanism for high performance machine learning SIMT processor

Aiming at the high-performance Single Instruction Multiple Threads (SIMT) processor for machine learning, a simple and efficient scheduling mechanism is proposed, which supports parallel operation of 4 blocks, 8 warps and 64 threads. The dynamic scheduling method combines two configurable scheduling modes. The design uses the synthesizable Verilog HDL language to implement its hardware circuit, and builds an FPGA-based verification platform to verify the function of the whole circuit. The results show that the scheduling mechanism designed in this paper meets the requirements of SIMT processor, and the overall performance of the processor is increased by 82.17%. The integrated maximum clock frequency can reach 181MHz on Xilinx's FPGA chip xcvu440-flga-2892-2-e.