Research on Single-Event Transients Sensitivity in Phase-Locked Loops Based on PDSOI Process

Single-event transients (SET) sensitivity of a Phase-Locked-Loops (PLL) based on 0.35 μm PDSOI process has been analyzed. By measuring the phase jitter of PLL's output, the impacts of SET and their occurring possibility have been evaluated. An optimized SET injection model was used in circuit level simulation to improve the accuracy of simulation prediction. The SET sensitive nodes and operating condition of circuit are analyzed, and the results show that frequency divider (DIV) and output Low Voltage Positive Emitter-Couple Logic (LVPECL) are the most sensitive sub-circuits, whose SET sensitivities are close related to their working condition. In the worst case, phase jitter can be up to about half of the output cycle. Analysis results would be helpful to the design of radiation hardening.