A Method Based on Configurable Random Test Generation for Multi-core Verification

As multi-core designs architectural complexity increases,the challenge of verification grows dramatically.Through analyzing the methods of simulation based verification of multi-core designs,in this paper we present a new method based on configurable random test generation to verify multi-core cache coherence.Configurable random test generation is used to generate specified instruction streams by controlling generation variables.The execution sequence of the instruction stream in multi-core design can be predicted exactly by using memory address accessing constraints and synchronization operation.Further more,the self-checking instruction groups are used to check the simulation results automatically.The experiment result shows that our method is efficient.