Design of a dual Slope ADC for wireless monitoring of electrocardiography

This paper presentsa fully on-chip fully-differential dual-slope ADC that can be used for low frequency bioelectrical signal processing, it uses two anti-integrating reference voltage for wide range input.The auto-zero technique is applied to reduce the offset of op-amp. Dynamic comparator and well-designed clock timing controller of the comparator are used to save more power. The timing controller is set to let the comparator have sleeping mode and working mode. The proposed 12 bit dual-slope ADC is implemented in 0.35 μm CMOS process, the ADC has sampling rate of 689 S/s under 6MHz clock, working at 2 V supply voltage, the ADC consumes 6 μA current. Simulation result shows that the effective number of bits (ENOB) for the ADC is 11.8 bit.