The Implementation of a High-Performance Blind Oversampling Clock Data Recovery Circuit

Design a blind oversampling clock and data recovery circuit with the filtering and shaping circuit.The circuit mianly contains parallel oversampling module、synchronization and adjustment module、filtering and shaping circuit、phase detector and encoding circuit、data selection module. The filtering and shaping circuit can effectively improve the mutations in the sampling data stream, so that the circuit has a higher ability to suppress noise and disturbing, combined with phase detector and encoding circuit, the clock and data recovery circuit can get a lower BER and shorter phase-locking time. The verification of FPGA shows that the clock data recovery (CDR) circuit can properly work in the data transfer rate of 100Mbps, the phase-locking time is 0 bit.