LIU Xue-zheng, ZHANG Sheng-bing, HUANG Xiao-ping. Design of a 32-bit Fast Adder for Short Vectors[J]. Microelectronics & Computer, 2010, 27(9): 40-44.
Citation: LIU Xue-zheng, ZHANG Sheng-bing, HUANG Xiao-ping. Design of a 32-bit Fast Adder for Short Vectors[J]. Microelectronics & Computer, 2010, 27(9): 40-44.

Design of a 32-bit Fast Adder for Short Vectors

  • This paper studies and designs a novel 32-bit short vectors fast adder for multimedia application.The adder, which is based on Sklansky Parallel-Prefix adder,by controlling the carry chain,realizes both of four and two paralleled addition operations,with 8-bit and 16-bit addends respectively.It also supports one addition operation with 32-bit addends, as well as the comparison operation between single-precision floating-point data.Synthesis shows that,compared with traditional design,the overall performance of our novel adder is better,with a circuit area approach and a timing improved by 10 percent.
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