Design and implementation of high performance SIMT processor for machine learning

Aiming at the problem of large data volume computing in machine learning, a high-performance SIMT (Single Instruction Multiple Threads) architecture processor was developed. Using a special four-stage pipeline structure, the circuit is described in a synthesizable Verilog HDL language, and multi-thread parallel computing of data is completed. The simulation verification platform was built on the xcvu440-flga2892-2-e FPGA of XiLinxVirtexUltraSacle series to verify the function of the whole circuit. The results show that the design circuit satisfies the multi-thread parallel processing mechanism. The SYNOPSYS Design-Compile is used for comprehensive verification in the SMIC 65 nm CMOS process standard cell library. The maximum operating frequency of the system clock is 370 MHz, and the maximum power consumption of the system is 4.251 mw.