Design and Implementation of a 65 nm CMOS Clock Generator

This paper introduces a clock generator intended for the use in a high-speed SoC design. Fractional division achieved through the employment of Delta-sigma modulation. Significantly suppression of quantization error, which is caused by the Delta-sigma modulation, obtained through the use of dithering and DAC compensation technology. Circuit design implemented based on a 65 nm CMOS process and the simulation result shows that the period jitter (rms) and the total power are 0.656 ps and 3.824 mW, respectively, when the output frequency is 1.2 GHz of a typical application.