One Design of Specified Reconfigurable Pipeline Signal Processing Core

Reconfigurable Pipeline Signal Processing Core (RPSC) improves the performance and flexibility of various applications by hierarchical reconfigurable architecture. The topology and interconnection of RPSC's basic pipelines are changed by coarse-grained static configuration method. The RPSC specified to signal processing algorithm can be configured to implement two applications: frequency measurement algorithm and array signal processing algorithm. Moreover, it is convenient and flexible to configure the parameters in two different algorithms, in which the resources are reused. Two algorithms implemented use parallel and pipeline architecture to meet the demands of flexibility, real-time and data throughput rate. Based on Xilinx Virtex-7 FPGA VC707 Evaluation Kit, the design is verified with frequency of 150 MHz. The reuse ratios of computing source and memory resource are 47.8% and 17.6%, respectively. The throughputs of frequency measurement algorithm and array signal processing algorithm are 7.2 Gb/s and 14.4 Gb/s respectively and they are enough to meet the requirement for applications. In the practical situation, it is possible to analyze and select suitable applications of different classes and complexity to improve the frequency, reuse ratio and flexibility.