Design and implementation of convolutional neural network processor based on RISC-V instruction set

A low power embedded convolutional neural network acceleration processor is designed and implemented in response to the growing demand for computational resources in convolutional neural networks and the difficulty of applying traditional hardware convolution acceleration schemes in power- and area-sensitive edge computation applications. The target processor based on the RISC-V instruction set architecture, extend four custom neural network instructions, and accelerates the processing on the hardware architecture. The convolutional neural network processor maximizes the reuse of the original RISC-V data path and functional modules, reducing additional resourceoverhead. The target processor is verified by the RISC-V official standard test set, and the MNIST handwritten data set is identified and tested, with a correct rate of 97.23%. The target processor occupies 0.34mm² area and consume 11.1μw/MHz dynamic power using TSMC 40nm technology. Compared with the correlation processor, it has certain advantages in area and power consumption.