Hardware Model Based Cache Design Space Exploration

In this paper, a hardware emulation method — RTL level models is used for CPU and cache controller, while circuit model for cache memory cell — is adopted to do research on cache performance and power.A more accurate design space, miss rate and energy trend influenced by cache parameters, is presented.Finally, CAM-based high-associativity cache is designed in this paper, and compared with RAM-based high-associativity cache.It shows that the average energy of CAM-based instruction cache and data cache is reduced by 35.16% and 30.68%, respectively.