A BIST Scheme of ADC in Mixed-Signal SoC

A BIST scheme that can both characterize the dynamic and static parameters of ADC in mixed-signal SoC are proposed in this paper. The proposed scheme can fully characterize the ADC under test by integrating test capability of both dynamic and static test uniformly in one BIST circuit. Elemental operative units and memories for analog stimulus generation and response analysis are well organized and reused to reduce hardware overhead to the minimum. The pro- posed scheme is implemented in FPGA thereby validates the viability of the design.