An intra-prediction dynamic reconfigurable implementation of early termination unit partitioning

The High Efficiency Video Coding (HEVC) intra prediction algorithm for the dedicated hardware has a large resource occupation, and the hardware resources cannot be reused and the flexibility is poor. A reconfigurable video array processor is proposed, which can dynamically map the intra prediction algorithm according to the characteristics of the current video sequence. Firstly, the characteristics of HEVC intra prediction algorithm and the feasibility of reconstruction are analyzed. The threshold of early termination of coding block partition is determined as the basis for processor hardware reconstruction. Second, the reconfigurable array processor is driven by the calculated parameters for hardware reconstruction. Finally, intra prediction algorithm mapping is performed on the reconstructed array processor. By performing Planar and DC prediction mode experiments on a 4×4 reconfigurable array, the results show that the resource is reduced by 65% compared with the dedicated hardware implementation method, and the latency is reduced by 32% compared with the multi-core processor implementation.