Energy-efficient nonvolatile SRAM design based on mltilevel RRAM

A novel energy-efficient nonvolatile static random access memory(nvSRAM)design utilizing the multi-level cell(MLC)characteristics of resistive RAM(RRAM)cell is proposed for frequent-off and instant-on applications. The multi-bit data store circuitry is designed to enable the storage of every two-bit SRAM data into a single 4-level MLC-RRAM to achieve low store energy with reduced number and suppressed average write current of RRAM devices. Simulation results show that high data access speed is maintained with the proposed MLC-nvSRAM circuit when performing the SRAM operations. As compared to the previously published SLC-nvSRAM cells, the store energy and break-even time of the proposed MLC-nvSRAM cell are reduced by up to 76.80% and 74.01%, respectively.