A MUX Structure Design for Soft Error Mitigation in FPGA

Field Programmable Gate Arrays (FPGAs) have been widely used in aerospace and industrial applications. However, the SRAM-based FPGAs can be easily influenced by soft error, such as the Single Event Upset (SEU) by energetic particles from aerospace. In this article, we focus on the MUX structure in FPGA, and propose a novel MUX design for SEU mitigation. MUX design takes advantage of the redundant configuration bits found in real FPGAs by re-encoding the MUX configuration bit for SEU immunity. The experimental results show that the MUX structure presented in this paper can fulfill a complete protection against SEU under a low area overhead.