The Design of MSK Demodulator Using Time-to-Digital Converter

A new MSK demodulator is designed and realized with Time-to-Digital Converter (TDC) technique in accordance to IEEE 802.15.4 standard. It consists of Limiter, TDC and Data Recovery Circuit. Limiter amplifies the input signal of demodulator to rail-to-rail. After that, TDC measures the frequency of the amplified signal by detecting the zero-crossing and converts it into binary code. Finally, the original transmitted data is recovered from the binary code by Data Recovery Circuit. The theoretical model of demodulator is given to analyze the affect factors of system performance. The demodulator is implemented in TSMC 0.18 μm CMOS technology with the layout area of 0.1 mm². The theoretical and practical simulation results simultaneously show that the proposed demodulator achieves PER of 1% with SNR of 8.7 dB and power consumption of less than 1 mW, which meets the requirement of low power and low cost.