A Low-Power Instruction Cache Design for Superscalar Microprocessors

To reduce the power consumption, three optimization strategies are proposed for the multi-bank and pipelined instruction cache in superscalar. The first technique is conditional amplifying based on cache way, which avoids sense amplifiers driving data from memory arrays in irrelated ways. The second one is dynamic voltage scaling based on cache line, which provides the normal operation voltage just for the active cache line and keeps all the other cache lines drowsy in a lower voltage. The last strategy is instruction recycling based on short loop program, which reuses ancient instructions to prevent redundant cache access. Experimental results show that this design methodology can reduce the total power of instruction cache by 72.4% and 84.3% respectively in SPEC and PowerStone benchmarks, and bring processor IPC loss by only 1.1% and 0.8% respectively, without any timing overhead.