A Hardened SRAM Cell-DDICE and Peripheral Circuits Design

The classic DICE unit possesses high efficiency of anti-SEU in the static state of SRAM, but it is incapable of resisting SET caused by single particle strike in the read-write cycle. This paper proposes a new structure Delay DICE (DDICE) based on DICE. It separates read and write lines on the basis of interlocking structure and add delay unit and delayed bit line to write data. This new memory cell has got the ability to immunize Single Event Transient in any working period besides anti-SEU. Furthermore a filtering unit is added to the decoding circuit which prevents writing or reading data to wrong storage cell when decoding circuit is hit by single particle. SRAM with this new structure will get a strong ability of anti-Single Event Effects and high security of data for the multiple aspects of hardening design.