Design and Performance Analysis of a Three-Operand Leading-one Prediction Algorithm Based on FPGA

In this paper, a method is adopted to deal directly with three-operand on FPGA platform and three operands complete prediction algorithm implementation is designed. This method can reduce the critical path delay and power consumption. The article focused on the design of three-operands encoding tree structure,and based on the pre-encoding rules on FPGA hardware verification platform, reasonable modular for system architecture, using hardware description language VerilogHDL to program some function module to optimize the design process and last the results are analyzed and verified.Compared with the design using the traditional algorithm,the one using the proposed algorithm can reduce the delay of the critical path by36.15%,and reduce power consumption by 39.20%.