Efficient Implementation for Digital Part of 24 Bit Audio Sigma-Delta DAC with Low Power

One area-efficient technique is applied to accomplish digital front-end of 24-bit audio digital-to-analog converter (DAC) with low power consumption and less area. For reducing hardware overhead and area, finite-impulse response (FIR) filter is implemented with optimized structure, improved non-recursive common sub-expression elimination, adders and registers reusability. Optimal 4^th order 3 bit sigma delta modulator overcomes the need of dither and relaxes the requirement of analog post filtering. The digital part is implemented in SMIC 40nm 1P6M process, the total core area is 0.058 mm². From the simulation of this digital part with the power supply of 1.1 V, the power consumption is 53 μW. At the same time, the peak signal to noise (SNR) achieves 146 dB, and THD is -150 dB.