The Mechanism and Implementation of Sampling Rapid Serial Signal in SerDes Technique

The sampling on rapid signal at the receiver is one of the key technolog.On the basis of sampling theory,a digital sampling model is set up and a general method of solving those questions is put forward.As an applicational instance,8-phase sampling clock is proposed. The clock, with 45 degrees' discrepancy between adjacent phases, samples 12.5 Gb/s rapid serial data coded in 8B/10B. In the sampling circuit of hardware,5-level flip-latch is employed. There are two level cascaded with CSA,one with CTOL flip-latch for two-line to one-line,one with CMOS D-type synchronization flip-latch for phase tune and one with CMOS D-type synchronization flip-latch The sampling has been implemented on 5 levels in logical design. The consequence is simulated and verified to be accurate.