Interrupt and NMI optimization in RISC-V processor based on vector table

In response to the problem of long interrupt response delay in Reduced Instruction Set Computer (RISC) -V processors with real-time requirements, this paper improves the calculation method of the interrupt service program address in interrupt response, extends the Control and Status Register (CSR) during Non-Maskable Interrupt (NMI) response, and proposes hardware vector interrupt and NMI-related CSR extension. The hardware vector interrupt improves the interrupt response speed and reduces the interrupt response delay. The NMI extension control register reduces the response delay of NMI and reduces the need for software to save the context. The correctness and performance of interrupt optimization were verified using VCS simulation. The simulation results show that the response time of hardware vector interrupt is shortened by 84.4%, and the response speed has improved sixfold compared to the original. The NMI extension control register reduces the response time by 31 clock cycles and the return time by 32 clock cycles.