The self-testing algorithm for DDR interconnect faults in information processing microsystem

In order to solve the problem of balancing test efficiency and test cost of various complex interconnect faults of Double Data Rate(DDR) devices in information processing microsystems, this paper aims at DDR typical interconnect fault modes and combines the Auto Test Equipment(ATE) test algorithm of a single memory device with the System Level Test(SLT) program of a board-level system. Based on the Field Programmable Gate Array(FPGA) device that comes with the system, the self-test of the DDR interconnection fault in the microsystem is realized, and the simulation verification of the typical algorithm is completed. Compared with single-chip testing using ATE testing machine or running test software through CPU, the FPGA embedding specific sub-test algorithm scheme adopted in this paper can achieve high coverage of typical DDR interconnection faults, test efficiency and the balance of test costs has been significantly improved.