PANG Y,YANG J B,WANG Y F,et al. An efficient FPGA implementation of a real-time multi-class classifier for small target[J]. Microelectronics & Computer,2024,41(3):118-127. doi: 10.19304/J.ISSN1000-7180.2023.0124
Citation: PANG Y,YANG J B,WANG Y F,et al. An efficient FPGA implementation of a real-time multi-class classifier for small target[J]. Microelectronics & Computer,2024,41(3):118-127. doi: 10.19304/J.ISSN1000-7180.2023.0124

An efficient FPGA implementation of a real-time multi-class classifier for small target

  • With the goal of improving real-time performance in recognizing and classifying small targets, and reducing the resource consumption of the recognition system, a simple and efficient Field Programmable Gate Array (FPGA)-based small target recognition and classification scheme is proposed in this paper. First the system through image preprocessing to remove image noise, and use the real-time performance of the parallel computing system. The processed image is then matched to the template to produce the recognition result. The designed template matching circuitry has lower hardware complexity and faster processing speed. The results of the experiment show that the recognition system proposed in this paper can process 137.5 frames at 680×480 image resolution, and has a strong performance in real time. At the same time, it consumes 9 Block Random Access Memory (BRAM) and 2 Digital Signal Processor (DSP), which is of great practical value in small target recognition and classification.
  • loading

Catalog

    Turn off MathJax
    Article Contents

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return