A low delay low power PWM comparator circuit design

A low delay and low power voltage type static Pulse Width Modulation (PWM) comparator based on HHGrace 0.35 μm BCD process is designed, which is mainly used in high frequency and low power switching power supply systems. The design includes a dynamic tail current source and an improved positive feedback amplifier to improve the high latency and power consumption of traditional Operational Transconductance Amplifier (OTA) comparators. The simulation results show that the system works stably in the supply voltage range of 1.2 - 5.0 V, the maximum rising edge delay is 35 ns, the maximum falling edge delay is 41 ns, the system supports the switching frequency of 6 MHz, the comparison accuracy is 8 mV, the offset voltage is 439 μV, and the static power consumption is only 2.5 μA (1.2 V) and 4.4 μA (5.0 V).