A design methodology for fast timing closure

Fixing timing in customized processors design is always a difficult task . In order to meet all timing requirements of WS_CPU with 14nm process, this paper proposes an efficient and reliable design methodology: (1) the new FCHT(Flexible Configurable H-Tree) implement even clock signal allocation and reduce routing time. Meanwhile, adopting the CCOPT (Clock Concurrent Optimization) technology to optimize the clock tree; (2) DCG (Design Compiler Graphical) mode and ICG (Integrate Clock Gating) technology are used in the synthesis phase to assess design risks to reduce the design iterative time of layout and routing. With this methodology, the setup time of WS_CPU can achieve to 108 ps at 1 GHz working frequency. Moreover, compared with the traditional balanced tree, flexible H-Tree and 3-level H-Tree, the total power of the chip in FCHT structure is reduced by 7.71%, 6.18% and 7.87%. And it outperforms the traditional balanced tree by saving 3156 min, the Flexible H-Tree by saving 5200 minutes,shortening the design cycle of the chip.