HONG Guangwei, CUI Chao, YU Zhiguo, GU Xiaofeng. Design and verification of bus bridge between TileLink and AXI4 based on RISC-V processor[J]. Microelectronics & Computer, 2022, 39(4): 100-108. DOI: 10.19304/J.ISSN1000-7180.2021.1052
Citation: HONG Guangwei, CUI Chao, YU Zhiguo, GU Xiaofeng. Design and verification of bus bridge between TileLink and AXI4 based on RISC-V processor[J]. Microelectronics & Computer, 2022, 39(4): 100-108. DOI: 10.19304/J.ISSN1000-7180.2021.1052

Design and verification of bus bridge between TileLink and AXI4 based on RISC-V processor

  • RISC-V is an open reduced instruction set architecture in recent years, and TileLink is a chip-scale interconnect standard designed for RISC-V. In order to use the existing AXI4 IP (Intellectual Property) resources flexibly in RISC-V processors, an efficient bus bridge design scheme between TileLink and AXI4 is proposed. A series of sub-modules match the transaction differences between Tilelink and AXI4, and complete the data transmission across protocols in the form of pipeline transmission, increasing the data throughput of the bus bridge. Different arbitration strategies are used to realize the conversion between different channels of the bus bridge. In the process of AXI4 bus response conversion, fixed-priority arbitration is used to preferentially convert read response, which improves the operating efficiency of the system. In the process of AXI4 bus write and read transactions conversion, round-robin arbitration is used to ensure the fairness of write and read transactions, balance the target channel bandwidth, and improve bus bandwidth utilization and system transmission efficiency. The functions of bus bridge are verified at the module level, by using Tilelink random test vectors. And by mounting the PCI Express root complex of AXI4 interface, the function of bus bridge is verified at the FPGA system level. The results show that the bus bridge can converse protocol correctly and greatly improve the system bandwidth utilization. The bus bridge is implemented in a SMIC 55 nm CMOS process. The frequency is 714 MHz and the area is 405×405 μm2 after physical design.
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