基于FPGA的万兆以太网链路的设计与实现
The design and implementation of 10 gigabit ethernet link based on FPGA
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摘要: 本文设计了基于FPGA的万兆以太网链路传输系统.对现有七层OSI模型进行简化, 设计了五层网络传输模型, 并深入研究了传输层、网络层和数据链路层.实现了完备的UDP/IP协议、ARP协议和万兆数据链路层MAC控制器, UDP/IP协议实现了数据的封装与解封, ARP协议解决了IP地址与MAC地址映射的问题, 方便大规模的系统级联.使用重复的CRC校验单元, 实现了CRC校验零延迟, 加快了数据的传输过程.基于Xilinx的Kintex UltraScale器件进行了系统设计实现, 并使用MC02开发板进行了系统功能测试.Abstract: Based on the FPGA hardware, this paper designs a 10 Gigabit Ethernet link transmission system. Simplifying the seven-layer OSI model, the paper designs a five-layer network transmission model and deeply studies the transport layer, network layer and data link layer. A complete UDP/IP protocol, ARP protocol and 10 Gigabit data link layer MAC controller are implemented. The UDP/IP protocol implements data encapsulation and decapsulation. The ARP protocol solves the mapping problem between IP address and MAC address, which is conducive to build a large-scale system. Using repeated CRC units, the paper implements CRC with zero delay, which speeds up the data transmission process. The system was designed and implemented on the Xilinx-based Kintex UltraScale device and the system function test was performed on the MC02 development board.