埋部分P+层背栅SOI高压器件新结构
A Novel Buried Partial P+ Layer SOI High Voltage Device Structure with a Back Gate
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摘要: 提出了一种埋部分P+层的背栅SOI (Buried Partial P+layer SOI, BPP+SOI) 高压器件新结构.部分P+层的引入不仅有效地增强了源端埋氧层电场, 而且还降低了源端PN结表面电场, 使器件击穿电压随背栅压的增加而大幅增加, 比导通电阻也显著降低.仿真结果表明, 在漂移区长度为150μm, 背栅压为650V时, BPP+SOI的耐压较常规结构提高了84.9%;在漂移区为120μm, 耐压相同的情况下, BPP+SOI的比导通电阻较常规结构降低了31%.Abstract: A Novel Buried Partial P+ Layer SOI High Voltage Device Structure with a Back Gate (BPP+SOI) is proposed. At the source side, the vertical electric field of the buried layer is increased and the surface electric field of PN junction is reduced due to the Partial P+ layer on the buried oxide of this structure; therefore, the breakdown voltage of the structure is greatly increased when the back gate bias is increased. Moreover, the specific on-resistance is reduced significantly. The simulation results show that the breakdown voltage of the BPP+SOI increases by 84.9 % at the 650V back gate bias and 150μm drift region length while the specific on-resistance decreases by 31% at the same breakdown voltage and 120μm drift region length.
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