高精度SRAM端口时序参数测量电路的设计与实现
Design and Implementation of a High-resolution SRAM Timing Parameters Measuring Circuit
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摘要: 对一种普通的数字时间转换器(Digital-to-Time Converter, DTC)进行了改进, 能实现对输入信号延时的两级调节, 一级粗调, 一级精调, 在SMIC 130nm工艺下, 调节范围为0~2.0ns, 调节精度达到5ps, 同时减少了一半的面积, 优化了结构的非线性误差.利用改进后的DTC结构, 设计了两种测量方案, 分别实现了对SRAM输入端口的建立时间、保持时间及输出端口的数据读取时间的测量.仿真结果表明, 该电路对SRAM各个端口时序参数测量的误差小于3.33%.Abstract: A common DTC(Digital-to-Time Converter)circuit structure has been optimized, it is able to achieve twostage adjustment levels, both coarse and specific level.With the SMIC 130 nm technology, the adjustment range of the DTC structure reaches 0 ~ 2.0ns and the resolution achieves 5ps.Meanwhile, the area of circuit is can be cut down by 50%, and non-linear error is optimized as well.Based on the improved DTC, two measuring schemes are designed to measure the setup time and hold time for input ports, and the data access time for output ports.The simulation result shows that the overall measurement error is less than 3.33%.
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