Abstract: Because of the simulation speed disadvantage, traditional Verilog/VHDL are not suitable to model multiprocessor. To implement fast modeling, The paper uses SystemC to model multiprocessor and gives the details about how to model CPU, share dm, semaphore, mailbox, spin lock. Through detailed analysis to the SystemC model, the performance bottle-neck can be found and redesigned. Using this as a foundation, one synthesizable Verilog model is implemented by translateing SystemC programs to Verilog programs manually. The simulation result shows that SystemC model can improve the simulation speed about 15 times faster than Verilog model, which is both easy to model and accurate in cycle based simulation.