基于LVDS的高速数据交换引擎IP核设计
Design of LVDS High-Speed Data Exchange Engine IP Core
-
摘要: 设计了一种基于LVDS的高速数据交换引擎IP核,并详细阐述了在FPGA上的实现原理和关键设计.该IP核能广泛适用于低速、高速FPGA中,测试结果表明, IP核的逻辑功能正确,可适应从spartan3A器件上时钟频率150MHz, 300Mb/s数据传输速率 (1位模式, 4位模式下达到1.2Gb/s),到Virtex6器件上时钟频率500MHz, 1Gb/s数据传输速率 (1位模式, 4位模式下达到4Gb/s).Abstract: This paper scheme out a high-speed data exchange Engine IP core with LVDS technique,and expatiate the implementation principle and key design in FPGA.This IP core can widely apply to the Low-speed,High-speed and SoC integration.the results show that it can get a clock frenquency about 150 MHz,300Mb/s of data transmission rate (1-bit mode,1.2Gb/s in 4-bit mode) in spartan3 Aand 500MHz,1Gb/s of data transmission rate (1-bit mode,4Gb/s in 4-bit mode) in Virtex6.
下载:
