Abstract: Reffering to the lower work speed of adaptive gradient lattice joint processing (GALJP) on FPGA caused by the algorithm's complexity, a pipeline optimzation approach based on the technology of delay leading transfer is proposed. By approximate treatment to the updated weight coefficients and errors in each section of lattice filter and transversal combiner, the critical path delay of GALJP is reduced greatly, and the relationship between the pipeline depth and work speed is obtained through the design of EDA softwores. Simulation results show that the work speed of the three-level pipelining filter had increased nearly 30% than that of original GALJP without changing the adaptive parameters, and the pipelined filter costed only additional 60% logic element (LE) hardware resource more than the latter.