赵启林, 李冰, 时美强, 熊军. 面向视频处理的粗粒度可重构单元设计[J]. 微电子学与计算机, 2010, 27(5): 82-86.
引用本文: 赵启林, 李冰, 时美强, 熊军. 面向视频处理的粗粒度可重构单元设计[J]. 微电子学与计算机, 2010, 27(5): 82-86.
ZHAO Qi-lin, LI Bing, SHI Mei-qiang, XIONG Jun. Design of a Coarse-grain Reconfigurable Cell for Video Processing[J]. Microelectronics & Computer, 2010, 27(5): 82-86.
Citation: ZHAO Qi-lin, LI Bing, SHI Mei-qiang, XIONG Jun. Design of a Coarse-grain Reconfigurable Cell for Video Processing[J]. Microelectronics & Computer, 2010, 27(5): 82-86.

面向视频处理的粗粒度可重构单元设计

Design of a Coarse-grain Reconfigurable Cell for Video Processing

  • 摘要: 针对视频处理算法,设计了一种面向视频处理的粗粒度可重构处理单元.它可以执行8位数据的加法、减法、乘法、乘加和求两数差的绝对值等操作,可以有效地支持高计算密度的视频处理算法.可重构处理单元使用Verilog设计,采用CMOS0.18μm工艺DC综合,面积为97913μm,关键路径为4.51ns,总的动态功耗为4.2mW.完成一次8×8像素块的2D-DCT算法和全搜索块匹配MAD算法分别需要10和15个时钟周期.

     

    Abstract: This paper presents VORC(Video Oriented Reconfigurable Cell),a coarse-grain reconfigurable cell optimized for video processing. The cell has been designed to provide a dense support for video processing 8-bit arithmetic operations such as addition,subtraction,multiplication,multiply-accumulation and absolute value of the difference. The cell has been descripted with verilog and synthsized under 0.18μm COMS proces with Synopsys Design Compiler. The area is 97 913μm2 and the critical path is 4.51nm and the total dynamic power is 4.2mW. The entire 8×8 2D-DCT and FSBM MAD respectively require 10 and 15 cycles.

     

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