Abstract: Due to the amount limitation of FPGA IO, there is little DDR storage can be used. Furthermore, the memory capacity is the restriction in the big data application. In this paper, we modify the DDR interface design, using various protocols to accomplish the high speed data transaction, improving the memory capacity efficiently. In the experiment we get 4 times more storage capacity by using little IO resource, and compare several protocols implementation in the design, providing a useful reference for serial interface-based DDR design.