Abstract: Asynchronous circuit was designed and verified by the Muller gate designed by HDL on FPGAs previously,and it was implemented with manual P&R to accomplish timing constraint,which is so complex.In this paper,the flow combining Balsa asynchronous circuits design platform and Xilinx FPGA P&R tools was perfected.The four phase dual-track handshake protocol was used to avoid the complex flow of manual P&R and this design has well performance of transplant.This paper focused on the design of the input circuit which follows the asynchronous handshake protocol and completed a behavioral level to board-level design and verification of the whole process.