Abstract: We propose an effective algorithm for converting VLSI design into weighted hypergraph which converts the VLSI partitioning problem into the hypergraph partitioning problem.The algorithm reads and traverses the hierarchical VLSI design of verilog language, converts the VLSI design into the compressed storage format (CSF) of hypergraph and saves as file storage format (FSF) of hypergraph.Furthermore, a VLSI/Hypergraph Converter (VHC) is proposed and implemented for VLSI partitioning problem.The VHC's flow diagram is also presented.Finally, the experiment and analysis show that the VHC can rightly convert the case of gate CPU into FSF of hypergraph and its objective is to improve the efficiency of VLSI partitioner by avoiding partitioning the netlist of VLSI directly.