Abstract: In this paper,the new problems of traditional clock design in the hierarchical mode were analyzed and a new method of clock design was proposed.A phase_sync signal was used as a bridge of the top and sub-design in this method.It effectively prevents the'damage'to the internal timing of subchip caused by the top-level timing closure.At the same time,the application of this method avoids reset design of clock divider circuit and reduces the difficulty of back-end timing closure.