Abstract: In this paper,a design for the transmitter system of muti-channel high speed SerDes is presented.It's realized in 65 nm CMOS process and the data rate of a single lane is 10 Gb/s.The data lane circuit consints of a full-rate MUX and a CML driver;The MUX is adopted the structure with TSPC latches and TSPC D-flip-flops (DFF) instead of CML circuits in the high speed stages to save power and area.The diver is made of CML structure,and a 4 tap feed-forward equalization (FFE) is applied in the driver to reduce the influence of ISI;Finally,the impedance matching circuit is used to avoid signal reflection in the channel.