Abstract: A low-cost 64 times down sampling digital decimation filter is designed to filter and extract the output stream of ∑△ ADC. In order to save the area and ensure stability, a two-decimation cascaded filter type is selected firstly. Secondly, the structure of the single-stage filter is optimized, and the folded transposition structure with less area is adopted; on this basis, the coefficient optimization and common term extraction of the coefficient multiplication and addition part are carried out. Finally, the circuit simulation and function verification are carried out with Modelsim. Through optimization, the cost of registers and adders can be reduced to 59% and 35% versus before optimization, which means the resource optimization rate can reach 41% and 65%. The digital decimation filter is implemented in SMIC 0.18 μm CMOS process. The operating voltage is 3.3 V, the chip area is 1.13 mm * 0.36 mm, and the power consumption is 5.3 mw. The results of chip function test show that the sigma delta ADC digital decimation filter works normally, and it is a design circuit that takes into account the area and power consumption.