Abstract: An optical receiver front-end circuit suitable for optical connect system was designed in a SMIC 0.18μm CMOS process. The transimpedance amplifier (TIA) and limiting amplifier (LA) are integrated in one chip. TIA uses regulated cascade (RGC) to boost bandwidth. LA uses second-order active feedback architecture and active inductor loads to improve the gain-bandwidth product (GBW). The circuit provides an overall gain of 85dB with a bandwidth of 4.36 GHz. The chip dissipates 144mW from a 1.8V supply with its area of 1.0×0.7mm².