10-WD类音频功放输出级电路的设计
A 10-W Class-D Audio Amplifier Output Stage
-
摘要: 基于CSMC 0.5μm 40V高压BCD工艺设计了一种适用于大功率D类音频功放的输出级电路.通过合理设置功率管栅驱的死区时间,避免了功率管的同时导通,并使总谐波失真(THD)低至0.05%;通过减缓功率管的栅驱信号边沿,减小了功率管上的尖峰电流,从而使电源上的毛刺电压减小到0.24V;通过对导通损耗和开关损耗的整体考虑,确定了最优的功率管尺寸,在合理的版图面积条件下,达到了93%的效率.Abstract: Based on pocess of CSMC 0.5μm 40V BCD, this paper presents an output stage for high power Class-D amplifier.The proper dead-time of gate drive is set to avoid the two power MOSFETs conducting at the same time and low 0.05% THD is achieved.By slowing down the edge variation of gate drive signal, the peak current of power MOS is reduced and the spike voltage of the supply is reduced to 0.24V.Considering both of conduction loss and switching loss, the optimum size of power MOS is confirmed.With reasonable layout area, the amplifier achieves 93% efficiency.
下载:
