Abstract: Aiming at the drawback of Modified Euclidean(ME) algorithm based RS decoder,this paper presents an area-efficient implementation of ME block using FPGA.Making full use of the idle resource of ME block,this implementation scheme adopts multiple structure by reducing the number of PE block from 2t to t.For reducing the hardware complexity and chip area,this paper applies this area-efficient ME block to the implementation of RS(255,239) decoder.Simulation and test result shows that the decoder based on this improvement can achieve the designed function and its throughput reaches 6.4Gbps while its hardware complexity is widely reduced.