10Gb/s自适应均衡器设计
A Novel Architecture for 10 Gb/s CMOS Adaptive Equalizer
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摘要: 提出了一种改进型的自适应均衡器结构，通过在自适应环路中引入频谱均衡技术，分离出随机性二进制数据中的高频与低频分量，并将二者之间的平均功率进行比较，产生表征信道衰减程度的电压信号，据此调整高频增益的大小.本次设计采用SMIC 0.13μm标准CMOS工艺，在1.2V电源电压下，能够对长度达80cm的FR4基板传输线进行有效的补偿，从而完成对10Gb/s随机性二进制数据的最优均衡.Abstract: An adaptive equalizer incorporates spectrum-balancing technique to obviate the using of slicers.This circuit compares the low and high frequency components of the data spectrum and adjusts the boosting accordingly.Realized in SMIC 0.13μm CMOS technology,this circuit achieves a data rate of 10 Gb/s while compensating the 80 cm FR4 transmission line from a 1.2 V supply.
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