NOC路由节点VLSI设计
VLSI Design of Router for Network on Chip
-
摘要: 基于wormhole交换策略和目的地址确定性路由算法, 采用三级流水线的结构实现了片上网络中的路由节点.该路由节点适用于Mesh和Torus拓扑, 并采用虚通道技术增加吞吐量.在Xilinx的FPGA上实现后可知, 该路由节点最高可工作在130 MHz的时钟频率上, 传输带宽为20.8Gb/s.Abstract: A router with 3-stage pipeline architecture is designed for network on chip (NOC) in this paper.It is used wormhole forwarding strategy and deterministic routing algorithm and supports both Mesh and Torus topology.In order to increase throughput, the virtual channels technology is also used.The NOC router is implemented on Xilinx Virtex2p XC2vp30 with a maximum clock frequency of 130MHz and transmission bandwidth of 20.8Gb/s.
下载:
