Abstract: RV32I, a processor that supports 32-bit basic instruction sets, is designed to support the new open Reduced Instruction Set Computer RISC-V instruction set. The memory devices of its peripheral circuits include Quick Memory, Cache Memory and Synchronous Dynamic Random Access Memory. This paper focuses on the design and implementation of the control element of RV32I. It uses the classic three-stage pipeline-via finite-state machine to support-fetch, decode and execute and uses the synthesizable Verilog HDL language to describe. And reserved the control element of interrupt and exception. Simulation results show that the control element can realize the the pipeline operation normal and stable.